Rapid development and application of the information technology, wireless mobile communications and information appliances in recent years have been increasing our dependence on electronics and have brought about prosperity for various display technologies and devices. Flat panel display devices are finding extensive use for their complete flatness, lightweight, slimness, higher energy efficiency and other advantages.
At present, in order to reduce the manufacturing cost of flat panel display devices and allow narrow bezels thereof, the gate-in-panel (GIP) technology is usually used to directly integrate gate drive circuits (i.e., GIP circuits) into flat display panels. Such a gate drive circuit includes multiple drive units for generating GIP signals at multiple levels.
Referring to FIG. 1, a partial view of a conventional flat panel display is illustrated. As shown in FIG. 1, this conventional flat panel display 100 includes a plurality of pixels arranged in a matrix (not shown), a plurality of scan lines (S1 to Sn) and a GIP circuit 10 comprising a plurality of cascaded drive units (not shown) for respectively generating and outputting GIP signals, wherein the GIP signals include a first-cascade GIP signal provided to the scan line for pixels in the first row, a second-cascade GIP signal provided to the scan line for pixels in the second row, . . . , and an n-th-cascade GIP signal provided to the scan line for pixels in the n-th row.
The pixels in the flat panel display 100 are gated based on the associated GIP signals in the scan lines, and correctness of the different GIP signals has a direct impact on the display quality of the flat panel display. Once a GIP signal from a certain cascade is incorrect, the corresponding pixels cannot be gated, leading to display anomalies on a display screen of the flat panel display 100 such as operation failure of the screen, incorrect display in a strip across the screen, or abnormal display of images subsequent to correct display of them.
However, the drive units in the conventional GIP circuit 10 are usually circuits of a so-called 10T3C structure which is complex and incorporates a relatively large number of thin-film transistors (TFTs). Additionally, the GIP signals generated by the drive units cannot be neatly pulled down from a high level to a low level.
Reference is now made to FIG. 2, a diagram showing simulated conventional GIP signals. As shown in the figure, a GIP signal from a certain cascade, after being raised to the high level, is pulled down to the low level but not neatly pulled down, and a GIP signal from the next cascade is also not neatly pulled down to the low level from the high level. This may cause ripples which are detrimental to the display quality of the flat panel display device.
Therefore, there is a need in the art for a GIP circuit that is simple in structure and can produce GIP signals able to be neatly pulled down from the high level to the low level.